ASUS ASMM User’s Manual
13
I. ASUS ASMM
I.ASUS
ASMM
Programming
Interface
ASR Enable/Disable Sequence and Test
The ASR function will be enabled by consecutively writing three I/O writes to the
ASR enable/disable register with data pattern of xxxx_0001b. After these I/O writes
are executed, bit 3 of the ASR status/control register will be set to “1” and bit 4 of the
ASR status/control register will become “0” when there is no I/O write to the ASR
trigger register within a pre-specified period of time. (The time period can be selected
through 2 mini-jumpers with 30-, 90-, 240-, 330-second options.) The system will get
a reset if the bit 1/Mode Select B of the ASR status/control register is set to “1” (nor-
mal mode). Otherwise, no system reset will be generated; the application can test the
function of the ASR circuit by polling bit 4 of the ASR status/control register without
writing to the ASR trigger register for the pre-specified time for checking whether it
becomes “0” or not. If it is not, the ASR is malfunctioning. If it is, the application can
then issue an I/O write to the ASR trigger register and wait for 30ms. Then bit 4 of the
ASR status/control register can be checked again to see if it has changed to “1”. If it
has, the ASR circuit is correct. Otherwise, the ASR function is not working.
After the ASR function is enabled, consecutively writing three I/O writes to the ASR
enable/disable register with data pattern “xxxx_0001” can disable the ASR function. It
can be verified by reading bit 3 of the ASR status/control register to check if it has
changed “0”. If it has, the ASR is disabled. Otherwise, the SMC card is malfunctioning.
Secure Mode Enable/Disable Sequence
The system will enter secure mode only when bit 2/Mode Select A of the ASR sta-
tus/control register is set to “1”, then two consecutive I/O writes to the ASR enable/
disable register with data pattern “xxxx_0001” and then another consecutive I/O
write to the ASR trigger register are completed. While the system is under secure
mode, the keyboard will be locked and reset button disabled.
Two consecutive I/O writes to the ASR enable/disable register with data pattern
“xxxx_0001” and then another consecutive I/O write to ASR trigger register will
bring the system out, unlock the keyboard and enable the reset button.
Early Access of ASR
Because the ASR needs more time to be reset (1 more second than the main system),
unexpected problems can occur if someone tries to access/test/arm the ASR in the
BIOS/application while the ASR is still under reset. So, a new status bit called “ASR
under reset” has been added to the ASR status/control register so that the BIOS/
application can poll this bit first to make sure the ASR is out of reset and free for
access. Before you access the ASR, you must test this bit and check the related ASR
setting (that is, the ASR setting is what you want it to be) as long as there is any
possibility that the ASR has been reset for some other reason. For the BIOS, this bit
must be tested before it can access/control the ASR.