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ASUS ASMM User’s Manual
11
I. ASUS ASMM
I.ASUS
ASMM
Programming
Interface
Programming Interface
LM 78
The LM78 address is fixed on I/O port 0x0290–0x0297 by default, as follows:
0x0290
Power On Self Test codes from ISA bus
0x0294
Power On Self Test codes from ISA bus
0x0295
The LM78 internal Address register
0x0296
Data register
For the relative programming interface, refer to the N.S. LM78 data sheet.
Automatic Server Restart
Four I/O ports are defined in this revision and are allocated on I/O space 0x0298–
0x029F by default. These 4 I/O ports are ASR status/control register, Chassis intru-
sion reset register, ASR trigger register, and ASR enable/disable register.
ASR Status/Control Register (0x0298/Read/Write)
Read (default value: 00x0001)
bit 7:6 Card revision ID
00
SMC rev 1.x
others
Reserved
bit 5
ASR under reset. Because ASR needs a much longer time to be reset, this bit
should be polled by the BIOS/application before it can be accessed. A “0” indi-
cates the ASR is under reset such that the BIOS/application must wait until it
becomes a “1”. A “1” means the ASR is now out of reset and free for access.
bit 4
ASR test output. Under test mode, a “0” indicates a timeout event occurred
as being too long without writing to the ASR trigger register.
bit 3
ASR enable or disable. A “0” depicts ASR function is disabled; a “1” indi-
cates the ASR is enabled. While ASR is enabled, if the ASR is not under test
mode, ASR trigger register must be written within a pre-specified time pe-
riod or the system will get a hard reset.
bit 2
Mode select A
“0”
Secure mode is disabled (default)
“1”
Secure mode is selected. The system will enter the secure mode (key-
board is locked, reset button is disabled) after a special I/O write se-
quence is executed.